OBJECTIVES:
Design and simulate a 4-bit Synchronous Up-Down Counter in Quartus II.
DESCRIPTION:
This project is an individual assignment. Students will work with Quartus II graphic design tool and simulator that was used in Project 1. The project covers design and simulation of sequential circuits, specifically, four-bit Up-Down counter.
GUIDELINES: Each student will turn in a report with the results of their design and simulation of the circuits accompanied with supporting files. The report should contain:
1) a) Title Page The title page should be a single page with only the following. information:
i) Course number with section
ii) Project title
iii) Your name and IDs
iv) The date the project is submitted.
v) A brief description of the project
b) Theory of operation: Explain how your circuit works, but do not give implementation details. This should be an expanded version of the introduction. That is to give a high-level description of what your circuits do and how they do it. For example, you could explain any algorithms you implemented, any conditions or restrictions the user must observe to use the circuits, and the high-level structure of your circuits at the block diagram level.
c) Design details: This subsection is where you can go into the details of your design. It should contain any logical expressions you use, any Karnaugh maps or algebraic simplifications you performed, and any tables or state diagrams for sequential circuits. It should explain design techniques if they are not self-explanatory. It should refer to the detailed documentation (such as schematic diagrams) explicitly. This section should also contain a description of any unusual problems you had with your designed solution and how you solved them.
d) Schematic Diagrams. Make sure all input and output connectors are labeled with the proper signal name. Add labels for any interior signals that appear in the written description of the circuit, especially those that appear in logical expressions.
e) The waveform resulting from the time simulation. Do as many simulations you consider so that you can show the functionality of the circuit. You should set the waveform in the same order of variables that you provide in the truth tables.
i) Use only functional simulation.
f) Analysis, including comments and conclusions.
2) For this second project, you will proceed with the design and simulation of a four-bit Up-Down counter; you will need to use Flip-Flops JK negative edge triggered 74112. The flip flops are available in .mf library. This flip flops come in Dual-Packages so all you need is two of them. Implementation with other class of devices, like 71LS161/163 will not be considered. You need to take into consideration the following parameters:
a) The simulations should use a clock of 25 MHz.
b) The counter must operate with Up_Down, to select the counting direction, clear, preset and clock inputs and the respective four outputs Qa, Qb, Qc, Qd.
c) The snapshots should show a complete count (from 0000 to 1111 and another for a count from 1111 to 0000) and should show uses of Asynchronous Clear and Preset.
Category: DIGITAL TECHNOLOGY
1) a) Title Page The title page should be a single page with only the following. information:
i) Course number with section
ii) Project title
iii) Your name and IDs
iv) The date the project is submitted.
v) A brief description of the project
b) Theory of operation: Explain how your circuit works, but do not give implementation details. This should be an expanded version of the introduction. That is to give a high-level description of what your circuits do and how they do it. For example, you could explain any algorithms you implemented, any conditions or restrictions the user must observe to use the circuits, and the high-level structure of your circuits at the block diagram level.
c) Design details: This subsection is where you can go into the details of your design. It should contain any logical expressions you use, any Karnaugh maps or algebraic simplifications you performed, and any tables or state diagrams for sequential circuits. It should explain design techniques if they are not self-explanatory. It should refer to the detailed documentation (such as schematic diagrams) explicitly. This section should also contain a description of any unusual problems you had with your designed solution and how you solved them.
d) Schematic Diagrams. Make sure all input and output connectors are labeled with the proper signal name. Add labels for any interior signals that appear in the written description of the circuit, especially those that appear in logical expressions.
e) The waveform resulting from the time simulation. Do as many simulations you consider so that you can show the functionality of the circuit. You should set the waveform in the same order of variables that you provide in the truth tables.
i) Use only functional simulation.
f) Analysis, including comments and conclusions.
2) For this second project, you will proceed with the design and simulation of a four-bit Up-Down counter; you will need to use Flip-Flops JK negative edge triggered 74112. The flip flops are available in .mf library. This flip flops come in Dual-Packages so all you need is two of them. Implementation with other class of devices, like 71LS161/163 will not be considered. You need to take into consideration the following parameters:
a) The simulations should use a clock of 25 MHz.
b) The counter must operate with Up_Down, to select the counting direction, clear, preset and clock inputs and the respective four outputs Qa, Qb, Qc, Qd.
c) The snapshots should show a complete count (from 0000 to 1111 and another for a count from 1111 to 0000) and should show uses of Asynchronous Clear and Preset.
OBJECTIVES:
1.
Expose the CET 3116 student to the new Digital Programmable Devices Technology such as Read Only Memories (ROM), Programmable Logic Arrays
(PLA), Complex Programmable Device (CPLD) and Field Programmable Gate
Array (FPGA).
2.
Provide the CET 3116 student with the opportunity of familiarizing with the modern
methodologies of Digital Design and the Automated Digital Design Environment.
3.
Allow student to gain experience with the automated tools for design and
implementation of real circuits.
DESCRIPTION
This project is an individual assignment. Students will work with the web edition Altera Quartus® version 14.1 II CAD system. The system can be downloaded for free from https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html
You need to design and simulate an improved version of the burglar alarm reviewed in class.
Altera Quartus® II CAD system will be used in the subsequent course projects.
GUIDELINES:
1.
Each student will turn in a report with the results of their design and simulation of the circuits. The report should contain:
i.
A brief description of the project with circuit layout (schematics), the
waveform resulting from the time simulation, and your analysis, including
expressions, Karnaugh maps, comments and conclusions.
ii.
You will use only functional simulation.
iii.
Discussion in how you would implement the circuit in real life and under
which considerations.
iv.
Attached and upload separately the Quartus II files: bdf, vwf, qpf. Each
project will be compiled and simulated by the instructor. Note: keep in
mind that if you submit any outcome not originated by your design, you
will not get any credit for the project which considerations.
2.
To download the Altera Quartus® II CAD system follow the directions given in the document Quartusinst.doc. You need to use your Daytona state College e-mail and create your Altera account. Just follow the instructions on how to get the license file and installation.
3.
Once Altera Quartus® II CAD system is installed watch the videos on QUARTUS II and follow the tutorial Quartus II Introduction Using Schematic Designs. It will guide you on how to do the first part of the project and gain knowledge on how to use Quartus II. You will include snapshots of the resulting circuit and waveform obtained by you.
4.
Proceed with the design and implementation of an Enhanced Burglar Alarm that controls the security in a residence with 2 windows and one door. The circuits mustbe implemented
using only NAND gates (refer to section 7-3 in the book). Use as guideline the circuit discussed in the class (Combinatorial Circuits: Minimization Part I) and reviewed in the videos of Quartus II. You need to include snapshots of the circuit and the waveform.
5.
The project will be evaluated considering the following aspects:
i.
Result correctness.
ii.
Report completeness.
iii.
Clarity of ideas.
iv.
Bonus points implementing with ALTERA boards DE2-115.
OBJECTIVES:
1.
Expose the CET 3116 student to the new Digital Programmable Devices Technology such as Read Only Memories (ROM), Programmable Logic Arrays
(PLA), Complex Programmable Device (CPLD) and Field Programmable Gate
Array (FPGA).
2.
Provide the CET 3116 student with the opportunity of familiarizing with the modern
methodologies of Digital Design and the Automated Digital Design Environment.
3.
Allow student to gain experience with the automated tools for design and
implementation of real circuits.
DESCRIPTION
This project is an individual assignment. Students will work with the web edition Altera Quartus® version 14.1 II CAD system. The system can be downloaded for free from https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html
You need to design and simulate an improved version of the burglar alarm reviewed in class.
Altera Quartus® II CAD system will be used in the subsequent course projects.
GUIDELINES:
1.
Each student will turn in a report with the results of their design and simulation of the circuits. The report should contain:
i.
A brief description of the project with circuit layout (schematics), the
waveform resulting from the time simulation, and your analysis, including
expressions, Karnaugh maps, comments and conclusions.
ii.
You will use only functional simulation.
iii.
Discussion in how you would implement the circuit in real life and under
which considerations.
iv.
Attached and upload separately the Quartus II files: bdf, vwf, qpf. Each
project will be compiled and simulated by the instructor. Note: keep in
mind that if you submit any outcome not originated by your design, you
will not get any credit for the project which considerations.
2.
To download the Altera Quartus® II CAD system follow the directions given in the document Quartusinst.doc. You need to use your Daytona state College e-mail and create your Altera account. Just follow the instructions on how to get the license file and installation.
3.
Once Altera Quartus® II CAD system is installed watch the videos on QUARTUS II and follow the tutorial Quartus II Introduction Using Schematic Designs. It will guide you on how to do the first part of the project and gain knowledge on how to use Quartus II. You will include snapshots of the resulting circuit and waveform obtained by you.
4.
Proceed with the design and implementation of an Enhanced Burglar Alarm that controls the security in a residence with 2 windows and one door. The circuits mustbe implemented
using only NAND gates (refer to section 7-3 in the book). Use as guideline the circuit discussed in the class (Combinatorial Circuits: Minimization Part I) and reviewed in the videos of Quartus II. You need to include snapshots of the circuit and the waveform.
5.
The project will be evaluated considering the following aspects:
i.
Result correctness.
ii.
Report completeness.
iii.
Clarity of ideas.
iv.
Bonus points implementing with ALTERA boards DE2-115.